Design of a Low Power Multiband Clock Distribution Circuit Using Single Phase Clock

The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since this is the only signal which has the highest switching activity. Normally for a multiband clock domain network we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase clock(TSPC) multiband network which will supply for the multi clock domain network. In this paper, a wide band 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 or 64/65/78/79 prescaler. A dynamic logic multiband flexible integer-n divider based on pulse swallow topology is proposed which uses a low power wide band 2/3 prescaler and a wide band multimodulus 32/33/47/48 or 64/65/78/79 prescaler. Since the multimodulus 32/33/47/48 or 64/65/78/79 prescaler has a maximum operating frequency of 6.2GHz, the values of P and S counters can actually be programmed to divide over the whole range of frequencies. However the P and S counter are programmed accordingly. The proposed multiband flexible divider also uses an improved loadable bit cell for swallow counter and consumes a power of 0.96 and 2.2mW. This project is highly useful and recommended for communication applications like Bluetooth, Zigbee, IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers which are proposed based on pulse swallow topology. This design is modelled using Verilog simulated tool „MODELSIM 6.4b‟ and implemented and synthesized using „Xilinx ISE 10.1‟.